(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly to a structure and fabrication method for making polysilicon resistors with stable high resistance for mixed signal (analog/digital) integrated circuits. A silicide extension on the polysilicon resistor provides 100 percent metal shielding that prevents hydrogen ions from permeating the resistor, thereby providing more stable high value resistors.
(2) Description of the Prior Art
Many integrated circuits utilize both analog and digital circuits on the same chip. CMOS circuits provide low voltage, low power consumption for digital applications, while bipolar transistors require higher voltage and provide high current gain capabilities. These bipolar/complementary-metal-oxide-silicon (BiCMOS) circuits for ULSI with minimum feature sizes, (e.g., less than 025 um) require high value resistors that occupy the minimal surface on the chip. Polysilicon resistors formed on the field oxide (FOX) are preferred over diffused resistors in the silicon substrate because the diffused resistors require junction isolation with high capacitance that increases the RC time constant and degrades circuit performance. Also, the polysilicon resistor can be integrated into the Field effect transistor (FET) process without significantly increasing the process complexity.
Unfortunately, after forming the polysilicon resistor and during subsequent processing to form the multilevels of metal interconnections, hydrogen can rapidly diffuse through the interlevel and intermetal dielectric insulating layers into the resistor. The hydrogen intrusion can then fill the trapping states at the polysilicon grain boundary, thereby causing reduction and fluctuation in the resistance. One method of avoiding this problem by the prior art is to use a metal shield, formed from the first level of metal interconnections, over the resistor to shield the resistor from the diffusing hydrogen. This is best understood with reference to the schematic top view in FIG. 1 and the cross-sectional view in FIG. 2. FIGS. 1 and 2 show a conventional polysilicon resistor 16, formed from a patterned polysilicon layer, over a field oxide 12. An interlevel dielectric layer 22 is deposited over the resistor 16, and contact holes 23 are etched and metal plugs 24 are formed in the contact holes at both ends of the resistor. The first level of metal interconnections 26 is formed to make electrical contact to the resistor over the metal plugs. In this conventional method, the metal 26 is also patterned to extend over the body of the resistor to prevent hydrogen diffusion into the resistor 16 during subsequent processing, as shown in the top view of FIG. 1. However, it is necessary to provide a minimum spacing S between the metal contacting the plugs 24 to prevent shorting between the contacts at both ends of the resistor. This provides a path for hydrogen diffusion through the interlevel dielectric layer 22 into the resistor. Therefore there is still a need to improve upon the prior art to further minimize this hydrogen diffusion into the resistor.
Several methods of forming high-resistive elements on an integrated circuit are described in the literature. In U.S. Pat. No. 5,462,894 to Spinner et al., a polysilicon layer is oxidized to form a thin polysilicon resistor having high resistance, and doped or silicide contacts at both ends of the resistor. In U.S. Pat. No. 5,356,826 to Natsume, and in U.S. Pat. No. 5,618,749 to Takahashi et al. methods are shown for concurrently forming a polysilicon resistor, a capacitor, and a MOSFET. U.S. Pat. No. 5,135,882 to Karniewicz teaches a method for making high-value internodal coupling resistors for SRAM formed from a second polysilicon layer and having silicide contacts. U.S. Pat. No. 5,168,076 to Godinho et al., and U.S. Pat. No. 5,705,436 to Chin et al. describe methods for making polysilicon load resistors for SRAM. U.S. Pat. No. 4,968,645 to Baldi et al. describes a method for forming an intermediate connecting level composed of polycide and polysilicon portions for forming low-resistive interconnections and resistors on an integrated circuit.
However, there is still a need in the semiconductor industry to provide stable, high-value polysilicon resistors that are immune from hydrogen intrusion during processing.
It is therefore a principal object of this invention to form stable, high-resistance-value polysilicon resistors for integrated circuits on semiconductor substrates.
It is another object of this invention to utilize a polycide extension on the polysilicon resistor that extends the metal shielding to 100% and thereby prevents hydrogen ions from diffusing through the oxide and into the polysilicon resistor.
Still another object of this invention is to integrate these improved polysilicon resistor structures into the integrated circuits while forming salicide field effect transistors (FETs), thereby providing a cost-effective manufacturing process.
In accordance with the objects of the invention, a method for fabricating improved polysilicon resistors for integrated circuits is described. The method and structure can be integrated with self-aligned silicide (salicide) FETs without significantly increasing processing complexity. In the prior art, a metal shield formed from the first metal layer is used to prevent hydrogen ions from diffusing through the overlying intermetal dielectric layer(s) and into the resistor causing variable and unstable resistance. Since the metal layer is patterned to make electrical connections to the ends of the resistor, the metal layer cannot completely cover the resistor because a separating space (S) or gap is required to make the two contacts to the resistor without electrical shorting. This prior art, therefore, does not provide 100% metal shielding from hydrogen intrusion into the resistor. This new resistor structure and method overcome the problem associated with prior art high-value resistors by including a polycide layer that extends under the separating space S and provides 100% shielding from hydrogen diffusion. This invention is compatible with traditional salicide process without creating additional process complexity.
The method for making polysilicon resistors and field effect transistors (FETs) begins by providing a semiconductor substrate. Field oxide regions, such as shallow trench isolation (STI), are formed surrounding and electrically isolating device areas for the FETs. A thin gate oxide is grown on the device areas for the FETs. A polysilicon layer is deposited on the substrate and a cap oxide is formed by thermally oxidizing the top surface of the polysilicon layer. Using a first photoresist ion implant block-out mask, the polysilicon layer is doped over the device areas, and a second photoresist ion-implant block-out mask is used to dope the polysilicon layer to a predetermined concentration for the polysilicon resistors over the field oxide regions. The polysilicon layer having the cap oxide layer is patterned to form gate electrodes on the device areas, and concurrently polysilicon resistors having a first end and a second end are formed on the field oxide regions. Next, lightly doped source/drain areas are formed by ion implantation adjacent to the gate electrodes in the device areas, while the resistors are protected from implantation by a photoresist block-out mask. An insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. Source/drain contact areas are formed adjacent to the sidewall spacers in the device areas by ion implanting while using a photoresist block-out mask to protect other areas of the substrate from implantation. The cap oxide is removed from the gate electrodes, and concurrently the cap oxide is patterned over the resistors removing a portion over the first ends of the resistors. A refractory metal layer, such as titanium (Ti) is deposited and annealed at a temperature of less than 700xc2x0 C. to form titanium silicide (TiSi2) on the gate electrodes, TiSi2 on the source/drain contact areas, and, by the method of this invention, a TiSi2 layer over the first ends of the polysilicon resistors. The unreacted Ti metal over the oxide surfaces on the substrate is selectively removed by etching in a solution of NH4OH, hydrogen peroxide (H2O2), and deionized water at room temperature, and then a second anneal of about 800xc2x0 C. is argon (Ar) is used to lower the TiSi2 sheet resistance and to stabilize the TiSi2 phase.
An interlevel dielectric layer is deposited over the FETs and over the resistors on the substrate and can be optionally planarized. Next, contact holes are etched in the interlevel dielectric layer including contact holes to the first and second ends of the polysilicon resistor. The contact holes to the first end are over and to the silicide layer on the resistors. The contact holes are then filled with metal plugs, such as tungsten (W). The first level of metal interconnections are formed next by depositing and patterning a metal layer, such as aluminum/copper (AlCu). The metal is also patterned to make electrical contact to the metal plugs. The patterned metal layer also extends over the polysilicon resistors to prevent hydrogen from diffusing through the interlevel dielectric layer and into the polysilicon resistors. A key feature of this invention is to pattern the metal layer so that the spacing between the metal contacts to the metal plugs making contact to the resistors at the first and second ends is aligned over the silicide layer. The silicide layer under the spacing S increases the shielding to 100% and therefore further protects the polysilicon resistor from hydrogen intrusion. The integrated circuit can now be completed by including additional levels of intermetal dielectrics and metal layers. During completion of the integrated circuit, by including additional intermetal dielectrics and metal layers, when hydrogen is generated the metal shielding prevents this hydrogen from diffusing into the resistor.